Demand for semiconductor devices providing higher integration densities and increased response speeds may continue to increase. Technologies of manufacturing a semiconductor device have thus been developed to increase integration densities, reliability, and response speeds.
More particularly dynamic random access memory (DRAM) devices are widely used. Each memory cell of a DRAM device may include one access transistor and one capacitor. As integration densities of a semiconductor device increase, a horizontal area of a substrate on which the capacitor is formed may be reduced. Forming a capacitor providing a high capacitance on a reduced area may thus be a technical challenge.
To increase a capacitance of a capacitor, a dielectric layer having a relatively high dielectric constant may be used and/or an effective area of a capacitor electrode may be increased. Stacked capacitor structures and trench capacitor structures have been developed to increase an effective area of the capacitor electrode. Moreover, stacked capacitor structures have been provided as cylinders. U.S. Pat. No. 6,136,643 discusses a method of forming a cylindrical capacitor. The disclosure of U.S. Pat. No. 6,136,643 is hereby incorporated herein in its entirety by reference.
A lower electrode of the cylindrical capacitor may be formed to have an increased height. As a height of a lower electrode is increased, however, an upper portion of a cylindrical lower electrode may lean or fall down thereby reducing yield due to contacts between adjacent lower electrodes. Increasing a height of a lower capacitor electrode may thus be limited.